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Way Prediction Approach Can Reduce Set-Associative Data Cache for Digital Signal Processors
Update time: 2016/11/23
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For embedded digital signal processors, cache memories are relative large compared to simple cores, thus caches consume a significant amount of the total power dissipation. At the same time, as embedded systems and mobile devices become more popular, the low power consideration has become an important design constraint as well as the high performance requirement.

To achieve low miss rates for typical applications, modern digital signal processor utilizes set-associative caches. Set-associative caches probe the tag and data arrays in parallel, and then select the data from the matching ways, which is determined by the tag comparison. At the time of reading the tag and data arrays, the matching way is not known. Consequently, conventional set-associative caches read all the ways but select only one of the ways, resulting in wasted power consumption. For example, a two-way set-associative cache discards one of the two ways on every access, wasting nearly 50% of the power consumption.

Researchers WANG Leiou and WANG Donghui from the Institute of Acoustics of the Chinese Academy of Sciences have recently proposed a way prediction approach to reduce set-associative data caches power consumption. The way prediction approach records necessary information and predicts the matching way prior to the cache access, instead of waiting on the tag array to provide the way number. The approach can effectively reduce power consumption because only the predicted way is accessed.

In the way prediction cache architecture, a Way Predict Module implements the way prediction function. And the tag needs to save into a separate register array, called a Tag Record Buffer. To predict the access way number, a Way Record Buffer is also added. The way record buffer records the saving way number of corresponding tag in the tag record buffer. For a two-way set-associative cache, the width of the way record buffer is two bits.

If the tag record buffer does not include an instruction tag value, the tag should be saved into the tag record buffer. At the same time, the corresponding bit in the way record buffer should be set to 1. If the tag record buffer already has this tag value and the saving way number of this tag differs from the corresponding bit in the way record buffer, the way record buffer should be updated. For example, a tag is saved in way 0 and way 1 of the cache, so way 0 bit and way 1 bit of the way record buffer are both set to 1.

When an instruction needs to look up the set-associative data cache, the tag record buffer should be probed. If there is a hit in the tag record buffer, the corresponding bits are 2'b10 in the way record buffer. It indicates that this tag only exists in way 0 of this cache, so the output signal Way0EnFlag and Way1EnFlag are 1 and 0, respectively. That is to say, this instruction only needs to access the way 0 tag and data memory of the data cache. If the tag record buffer includes the tag of this instruction and the corresponding bits are 2'b11 in the way record buffer, or the tag record buffer does not include the tag of this instruction, the output signal Way0EnFlag and Way1EnFlag are both 1. In other words, the two ways of this set-associative data cache all need to be accessed.

The key to power reduction is to pinpoint the matching way without probing all of the ways. This research has derived a way prediction method to reduce level 1 set-associative data cache dynamic power while maintaining high performance. It is demonstrated that the proposed method provides a reduction in power of up to 18.97% and 14.70% on average, respectively, with negligible area overheads.


WANG Leiou, WANG Donghui. Way Prediction Set-Associative Data Cache for Low Power Digital Signal Processors. The 13th IEEE International Conference on Signal Processing (November 6th to 9th, 2016, Chengdu, China).


WANG Leiou

Institute of Acoustics, Chinese Academy of Sciences, 100190 Beijing, China


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